1. Field of the Invention
The present invention is related generally to a memory system, a memory device, a memory controller and method thereof, and more particularly to a memory system, a memory device, a memory controller for reducing power consumption and method thereof.
2. Description of the Related Art
FIG. 1 illustrates a conventional memory system 100 with a center tap termination (CTT). The conventional memory system 100 may include a bus line 15 connected between a transmitter 11 and a receiver 13. The bus line 15 may be terminated at a termination voltage Vtt which may correspond to half of a power supply voltage VDD. Thus, the bus line 15 may be maintained at the reduced level of VDD/2 during a standby period without data transmissions. Noise generated on the bus line 15 (e.g., during the standby period) may be interpreted as a signal transition on the bus line 15 depending on a sensitivity of the receiver 13.
Referring to FIG. 1, the receiver 13 may be a memory device and the transmitter 11 may be a memory controller. Alternatively, the receiver 13 may be a memory controller and the transmitter 11 may be a memory device.
Referring to FIG. 1, if the receiver 13 misinterprets the noise on the bus line 15 as a signal transition, the misinterpretation of the signal transition may cause the receiver 13 to function erroneously. In order to compensate for errors in signal recognition, the receiver 13 may maintain a received signal level for a period of time before a driver of the transmitter 11 initiates a signal transition. In addition, the receiver 13 may wait until after the period of time before again interpreting the signal level on the bus line 15 to detect a signal transition. However, performance of the conventional memory system 100 may deteriorate (e.g., due to transmission delays) as the period of time increases.
FIG. 2A is a timing diagram illustrating a conventional dual data rate (DDR) synchronous dynamic random access memory (DRAM) during a write operation.
Referring to FIG. 2A, a deterioration in the DQS bus line may be reduced by inputting the data strobe signal DQS synchronously with a clock signal CK during the write operation. In an example, the conventional DDR synchronous DRAM may operate according to a well-known tDQSS protocol. Accordingly, the conventional DDR synchronous DRAM may interpret a signal transition of the data strobe signal DQS in part by counting a number of clock cycles after receiving a write command.
FIG. 2B is a timing diagram illustrating the conventional DDR synchronous DRAM of FIG. 2A during a read operation.
Referring to FIG. 2B, the conventional DDR synchronous DRAM may output data in synchronization with the clock signal CK using a delay locked loop (DLL) such that a memory controller may estimate an arrival time for the output data at the memory controller (e.g., receiver 13, transmitter 11, etc.). The conventional DDR synchronous DRAM may thereby reduce a number of clock cycles to output a delay variation tDQSCK by using the DLL in the read operation. However, the DLL may increase a power consumption of the conventional system 100.